The present invention relates generally to systems and methods for storage devices, and specifically to improving performance of non-volatile memory devices.
Solid-state memory is ubiquitously used in a variety of electronic systems including, for example, consumer electronic devices (e.g., cellular phones, cameras, computers, etc.) and in enterprise computing systems (e.g., hard drives, random access memory (RAM), etc.). Solid-state memory has gained popularity over mechanical or other memory storage techniques due to latency, throughput, shock resistance, packaging, and other considerations. Among these non-volatile memory devices, NAND flash memory devices are popular due to low manufacturing cost for a high degree of integration.
Flash-memory based solid state disk (SSD) system often employ parity bits for error detection correction. In some conventional system, data bits associated with a bit line are often grouped in the calculation of a parity bit. The inventors have observed that, in some NAND drives, certain bit lines can have much higher bit error rate (BER) compared with other bit lines across word lines during the life of the drive. During chip-kill recovery, multiple word line failures cannot be recovered due to errors happening at same locations due to bit line failures.
In the past, interleavers, which is a device that performs an interleaving function to alter the sequence of selected data, have been proposed to improve the effectiveness of error detection using parities. For example, in one conventional interleaver, the parity is encoded by grouping data bits in a diagonal fashion. However, the inventors have observed that sequential bit lines failures cannot be recovered through a diagonal interleaver. Therefore, there is a need for improved interleavers for more effective error detection and correction.